The above-mentioned U.S. Pat. No. 4,295,209 late programming an IGFET ROM by ion implantation. By IGFET, we mean an insulated gate field effect transistor. The ROM comprises an orderly array of such transistors. The IGFETs are ordinarily arranged on a common silicon substrate in a pattern such that the gates of individual transistors are aligned in a number of parallel input rows. The drains of individual devices are aligned in a plurality of parallel columns. In a typical array of horizontal-type IGFETs, all IGFET drains can be contacted by a metallization pattern of parallel conductor output strips that overlie and, in plan view, are orthogonal to a pattern of parallel polycrystalline silicon gate input strips.
The aforementioned U.S. Pat No. 4,295,209 discloses programming the ROM by ion implantation through the polycrystalline silicon gate strips just before metallization, using a reflowable glass layer as a mask. In substance, all ROM gates are potentially active when the polycrystalline silicon gate strips are defined. A blanket silicon nitride coating is applied over all the polycrystalline silicon gate strips, and contact openings etched in it. A blanket reflowable glass coating is applied over the silicon nitride coating, and corresponding contact openings etched in it. However, concurrently, ion implant windows are also etched in the glass coating, over selected ROM gates. No additional masks are needed to perform the ion implantation since two masks are ordinarily needed anyway, to etch first through the glass and then through the underlying thermal oxide. The silicon nitride coating provides an insulating coating over the gate strip portion exposed within the ion implant window. Accordingly, metal drain strips can be applied over the glass in the usual manner. They can pass directly over the selected gate ion implant windows without electrically shorting to the gate strip in the window. Thus, not only is the late programming achieved but high ROM layout density is preserved.
On the other hand, in U.S. Pat. No. 4,295,209 the metal drain strips and the gate strip portions overlap within the ion implant windows with only a thin layer of dielectric therebetween. This generates a parasitic capacitance. In small ROM arrays the cumulative effect of this parasitic capacitance is not particularly significant. However, in large ROM arrays it can accumulate sufficiently to significantly slow down ROM operating speed.
We have now discovered how to minimize this parasitic capacitance but still obtain late programming, without increasing ROM size. In the aforementioned patent application Ser. No. 268,090 we propose to obtain both minimum parasitic capacitance and high ROM density by applying the U.S. Pat. No. 4,295,209 programming process to a ROM of unique configuration. In the aforementioned patent application Ser. No. 268,088 we propose using a silicon nitride etch mask as an ion implantation mask, whereby the subsequently applied phosphosilicate glass layer need not be removed over IGFET channels, to minimize parasitic capacitance. In the aforementioned patent application Ser. No. 268,086, we propose to program before the glass layer is applied by using an enhancement contact mask in combination with a second level polycrystalline silicon layer. In the programming technique of the present patent application, we propose to program using a second level of polycrystalline silicon in still a different way. The two programming techniques of Ser. No. 268,086 and the present application are particularly useful in making integrated circuits that would otherwise incorporate a second level of polycrystalline silicon for other purposes. In such instance, these techniques provide programming capability late in the process of manufacture without (a) adding another mask to the number of masks already needed to produce that product, (b) altering conventional processes, (c) expanding ROM size, or (d) decreasing ROM speed.